1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device equipped with a fusing portion which will be cut for defect relief, and more particularly to a method of fabricating a semiconductor device which forms an opening for easily cutting the fuse portion.
2. Description of the Prior Art
Generally, semiconductor devices in which elements such as transistors are integrated on a semiconductor substrate are subjected to wafer test before packaging to test whether it can carry out a prescribed operation. In this case, even when a failure chip with poor elements is found in the test, in order that the chip can carry out a normal operation without being fabricated again, a spare element previously formed in the same chip is substituted for the poor element. Such a technique has been commonly adopted to relieve the failure chip. Further, when a poor element is found in a memory array section, another block unit in a spare memory cell array is substituted for the block unit incorporating the poor element. The spare element is substituted for the poor element in such a manner that a fuse formed as a part of wiring is physically cut. For example, the semiconductor device is provided with a spare memory array as well as a memory array section. In such a structure, when a row decoder or column decoder for selecting each block receives an address signal selecting a block incorporating a poor element, a fuse is cut. Thus, without accessing the poor block, the spare block in place of it will be accessed.
The fuse can be cut by several methods. A method which has been widely adopted is laser trimming in which the fuse is molten and cut by laser irradiation. FIGS. 17A to 17C are sectional views of a semiconductor device which show the conventional method of laser trimming. In FIG. 17A, reference numeral 1 denotes a semiconductor substrate; 2 a first inter-layer insulating film formed on the semiconductor substrate; 3 a fuse portion formed on the first inter-layer insulating film; 4 a second inter-layer insulating film formed on the fuse portion 3 and the first inter-layer insulating film 2; and 5 a wiring layer serving as an electric pad formed on the second inter-layer insulating film 4.
As seen from FIG. 17B, the second inter-layer insulating film 4 is selectively removed by etching to form an opening above the fuse portion 3. In this step, the circuit formed on the semiconductor substrate is subjected to wafer test. A test signal is supplied through the wiring layer (electrode pad) 5. When it is found as a result of test that the fuse portion 3 must be cut, the fuse portion 3 is cut by irradiation of laser light rays 7 through the opening 6. Thereafter, as seen from FIG. 17C, a passivation film 8 serving as a final protection film is formed on the entire surface of the second inter-layer insulating film 4 and in the opening 6. Further, another opening 9 is made in the passivation film 8 by etching so that the electrode pad 5 is exposed.
The opening 6 is formed in order to reduce the thickness of the insulating film on the fuse portion 3 to a degree that the fuse portion 3 can be easily cut by irradiation of the laser light rays 7. In this case, in order to form the opening 6, a step of etching a resist formed using a photomask is required. For this purpose, the second inter-layer insulating film 4 is etched so that a contact hole is formed at the portion not shown of the second inter-layer insulating film 4 and the opening 6. Thus, the normal contact hole made in the inter-layer insulating film and the opening 6 can be formed in the same step using the same mask. For example, Postexamined Japanese Patent Pubication 4-79138 discloses that as shown in FIG. 18, in the same PSG film a, a contact hole b brought into contact with the source/drain regions c of an MOS transistor and an opening d formed on the fuse portion e on a field layer f can be formed simultaneously. A protection layer q is formed on the fuse portion e.
The technique described above has the following drawbacks. Where the contact hole b and fuse portion e are formed simultaneously, the fuse portion e is exposed. Exposure of the fuse portion e may lead to its break because of an accidental cause. In order to prevent this, a protection film q is previously formed on the fuse surface as shown in FIG. 18 thereby to prevent exposure of the fuse surface. In the above reference, a protection film q having a double layer structure composed of a polysilicon layer and a molybdenum silicide layer is formed on the fuse surface. However, this requires an additional step of forming the protection film. Further, in the above reference, the protection film g is formed of the same material and in the same step as the gate electrode of an MOS transistor. However, in the multi-layered structure of a semiconductor device, the fuse portion is formed on a more upper layer so that it can be easily broken. For this reason, the protection film cannot be necessarily formed simultaneously with the gate electrode.